1. Field of the Invention
The present invention generally relates to computer systems, particularly to a method of improving the performance of a computer system having a memory hierarchy which includes one or more cache levels, and more specifically to a method of using speculative loads for L3 caches with command aborts to lower memory latency.
2. Description of Related Art
The basic structure of a conventional computer system 10 is shown in FIG. 1. Computer system 10 may have one or more processing units, two of which 12a and 12b are depicted, which are connected to various peripheral devices, including input/output (I/O) devices 14 (such as a display monitor, keyboard, and permanent storage device), memory device 16 (such as random access memory or RAM) that is used by the processing units to carry out program instructions, and firmware 18 whose primary purpose is to seek out and load an operating system from one of the peripherals (usually the permanent memory device) whenever the computer is first turned on. Processing units 12a and 12b communicate with the peripheral devices by various means, including a generalized interconnect or bus 20. Computer system 10 may have many additional components which are not shown, such as serial and parallel ports for connection to, e.g., modems or printers. Those skilled in the art will further appreciate that there are other components that might be used in conjunction with those shown in the block diagram of FIG. 1; for example, a display adapter might be used to control a video display monitor, a memory controller can be used to access memory 16, etc. Also, instead of connecting I/O devices 14 directly to bus 20, they may be connected to a secondary (I/O) bus which is further connected to an I/O bridge to bus 20. The computer can have more than two processing units.
In a symmetric multi-processor (SMP) computer, all of the processing units are generally identical, that is, they all use a common set or subset of instructions and protocols to operate, and generally have the same architecture. A typical architecture is shown in FIG. 1. A processing unit includes a processor core 22 having a plurality of registers and execution units, which carry out program instructions in order to operate the computer. An exemplary processing unit includes the PowerPC.TM. processor marketed by International Business Machines Corp. The processing unit can also have one or more caches, such as an instruction cache 24 and a data cache 26, which are implemented using high speed memory devices. Caches are commonly used to temporarily store values that might be repeatedly accessed by a processor, in order to speed up processing by avoiding the longer step of loading the values from memory 16. These caches are referred to as "on-board" when they are integrally packaged with the processor core on a single integrated chip 28. Each cache is associated with a cache controller (not shown) that manages the transfer of data between the processor core and the cache memory.
A processing unit 12 can include additional caches, such as cache 30, which is referred to as a level 2 (L2) cache since it supports the on-board (level 1) caches 24 and 26. In other words, cache 30 acts as an intermediary between memory 16 and the on-board caches, and can store a much larger amount of information (instructions and data) than the on-board caches can, but at a longer access penalty. For example, cache 30 may be a chip having a storage capacity of 256 or 512 kilobytes, while the processor may be an IBM PowerPC.TM. 604-series processor having on-board caches with 64 kilobytes of total storage. Cache 30 is connected to bus 20, and all loading of information from memory 16 into processor core 22 usually comes through cache 30. Although FIG. 1 depicts only a two-level cache hierarchy, multi-level cache hierarchies can be provided where there are many levels of interconnected caches.
A cache has many "blocks" which individually store the various instructions and data values. The blocks in any cache are divided into groups of blocks called "sets" or "congruence classes." A set is the collection of cache blocks that a given memory block can reside in. For any given memory block, there is a unique set in the cache that the block can be mapped into, according to preset mapping functions. The number of blocks in a set is referred to as the associativity of the cache, e.g. 2-way set associative means that for any given memory block there are two blocks in the cache that the memory block can be mapped into; however, several different blocks in main memory can be mapped to any given set. A 1-way set associate cache is direct mapped, that is, there is only one cache block that can contain a particular memory block. A cache is said to be fully associative if a memory block can occupy any cache block, i.e., there is one congruence class, and the address tag is the full address of the memory block.
An exemplary cache line (block) includes an address tag field, a state bit field, an inclusivity bit field, and a value field for storing the actual instruction or data. The state bit field and inclusivity bit fields are used to maintain cache coherency in a multi-processor computer system (indicate the validity of the value stored in the cache). The address tag is a subset of the full address of the corresponding memory block. A compare match of an incoming address with one of the tags within the address tag field indicates a cache "hit." The collection of all of the address tags in a cache (and sometimes the state bit and inclusivity bit fields) is referred to as a directory, and the collection of all of the value fields is the cache entry array.
When all of the blocks in a congruence class for a given cache are full and that cache receives a request, whether a "read" or "write," to a memory location that maps into the full congruence class, the cache must "evict" one of the blocks currently in the class. The cache chooses a block by one of a number of means known to those skilled in the art (least-recently used (LRU), random, pseudo-LRU, etc.) to be evicted. If the data in the chosen block is modified, that data is written to the next lowest level in the memory hierarchy which may be another cache (in the case of the L1 or on-board cache) or main memory (in the case of an L2 cache, as depicted in the two-level architecture of FIG. 1). By the principle of inclusion, the lower level of the hierarchy will already have a block available to hold the written modified data. However, if the data in the chosen block is not modified, the block is simply abandoned and not written to the next lowest level in the hierarchy. This process of removing a block from one level of the hierarchy is known as an "eviction". At the end of this process, the cache no longer holds a copy of the evicted block.
In an SMP system with CPUs running at very high frequencies, system performance can be highly sensitive to main memory latency. One method to reduce latency is to use an L3 cache which is shared by multiple CPUs in the system. Since many of today's CPUs have fairly large L2 caches, the shared cache (L3 cache) must be very large to have a marked impact on system performance. Unfortunately, large L3 caches built from static RAM (SRAM) can be quite expensive. A more cost-effective approach is to use synchronous dynamic RAM (SDRAM). The primary drawback with SDRAM is a longer latency and a cycle time of a given memory bank, which can be ten times or so greater than that for high speed SRAM. The cycle time problem can be alleviated by employing many banks in the L3 cache such that the probability of accessing a busy bank is low. However, the latency is still fairly high, and thus the access should start as soon as possible.
In an SMP system, load requests coming from a given CPU can be satisfied (i) by another CPU if the memory value is held in one of the CPU's caches (e.g., held in a modified or exclusive coherency state using a MESI coherency protocol), (ii) by main memory, or (iii) by a shared cache (in this example a level 3 or L3 cache). One method to reduce latency of data supplied by the L3 cache is to access L3 data speculatively. In other words, the L3 data array is accessed in parallel with the directory and before the transaction snoop responses are known from the other CPUs. This approach can have the advantage of getting the data to the requesting CPU in the minimum amount of time in a system with low system bus utilization. However, when the system is highly utilized, there can be a significant amount of L3 data bandwidth wasted on L3 misses, or hits to modified data in another CPU's L2 cache. The net effect of the increased bandwidth usage can actually be higher average latency. To avoid this problem, the L3 cache access can be delayed until after the directory lookup and snoop responses are known. However, serially accessing the directory can also add a non-trivial amount of latency to data sourced by the L3 cache.
In light of the foregoing, it would be desirable to devise an improved method of using speculative accesses to an L3 cache to obtain low latency loads, wherein the data transfer phase could be aborted to prevent L3 misses and/or L2 modified data snoop hits from squandering precious L3 data bandwidth. It would be further advantageous if the method were able to compensate for the possibility that the speculative accesses to the L3 cache might result in more overall L3 activity.